Opportunities for radio frequency nanoelectronic integrated circuits using carbon-based technologies

This thesis presents a body of work on the modeling of and performance predictions for carbon nanotube field-effect transistors (CNFET) and graphene field-effect transistors (GFET). While conventional silicon-based CMOS is expected to reach its ultimate scaling limits during the next decade, these two novel technologies are promising candidates for future high-performance electronics. The main goal of this work is to investigate on the opportunities of using such carbon-based electronics for RF integrated circuits. This thesis addresses 1) the modeling of noise and process variability in CNFETs, 2) RF performance predictions for CNFETs, and 3) an accurate GFET compact model. This work proposes the first CNFET noise compact model. Noise is of primary importance for RF applications and its description significantly increases the insight gained from simulation studies. Furthermore, a CNFET variability model is presented, which handles tube synthesis and metal tube removal imperfections. These two model extensions have been added to the Stanford CNFET compact model and allow for the variability-aware RF performance assessment of the CNFET technology. In continuation, comprehensive RF performance projections for CNFETs are provided both on the device and circuit level. The overall set of ITRS RF-CMOS technology requirement FoMs is determined and shows that the CNFET performs excellently in terms of speed, gain, and minimum noise figure. Furthermore, for the first time FoMs are reported for the basic RF building blocks low-noise amplifier and oscillator. In addition, it is shown that CNFET downscaling yields significant performance improvements. Based on these analyses it is confirmed that the CNFET has the potential to outperform Si-CMOS in RF applications. A third key contribution of this thesis is the development of an accurate GFET compact model. Previous compact models simplify several physical aspects, which can cause erroneous simulation results. Here, an accurate yet simple mathematical description of the GFET’s current-voltage relation is proposed and implemented in Verilog-A. Comprehensive error analyses are done in order to highlight the advantages of the new approach. Furthermore, the model is verified against measurement results. The developed GFET model is an important step towards better understanding the characteristics and opportunities of graphene-based analog circuitry

An efficient algorithm to calculate intrinsic thermoelectric parameters based on Landauer approach

The Landauer approach provides a conceptually simple way to calculate the intrinsic thermoelectric (TE) parameters of materials from the ballistic to the diffusive transport regime. This method relies on the calculation of the number of propagating modes and the scattering rate for each mode. The modes are calculated from the energy dispersion (E(k)) of the materials which require heavy computation and often supply energy relation on sparse momentum (k) grids. Here an efficient method to calculate the distribution of modes (DOM) from a given E(k) relationship is presented. The main features of this algorithm are, (i) its ability to work on sparse dispersion data, and (ii) creation of an energy grid for the DOM that is almost independent of the dispersion data therefore allowing for efficient and fast calculation of TE parameters. The inclusion of scattering effects is also straight forward. The effect of k-grid sparsity on the compute time for DOM and on the sensitivity of the calculated TE results are provided. The algorithm calculates the TE parameters within 5% accuracy when the K-grid sparsity is increased up to 60% for all the dimensions (3D, 2D and 1D). The time taken for the DOM calculation is strongly influenced by the transverse K density (K perpendicular to transport direction) but is almost independent of the transport K density (along the transport direction). The DOM and TE results from the algorithm are bench-marked with, (i) analytical calculations for parabolic bands, and (ii) realistic electronic and phonon results for $Bi_{2}Te_{3}$.Comment: 16 Figures, 3 Tables, submitted to Journal of Computational electronic

A compact noise model for carbon nanotube FETs

This paper focuses on the development of a compact noise model for radiofrequency (RF) carbon nanotube field-effect transistors (CNFET). The noise mechanisms in these devices are discussed and the impact of the different noise sources is analyzed. For the RF-CNFET under investigation a mínimum noise figure NFmin = 0.104 dB at 60 GHz is predicted. Our model is usable with conventional circuit simulators, which provides a basis for further investigations on CNFET-based RF Building blocks.Peer Reviewe

Radio-Frequency Performance of Carbon Nanotube-Based Devices and Circuits Considering Noise and Process Variation

This paper provides a global overview of the radiofrequency (RF) performance potential of carbon-nanotube field-effect transistors (CNFET), which for the first time includes the impact of noise. We develop noise and manufacturing process variability extensions for the Stanford CNFET compact model, implemented in Verilog-A and compatible with conventional circuit simulators. CNFET figures-of-merit (FoM) are determined both on the device and on the circuit level. Compared to silicon technology, CNFET devices show much better performance in terms of most of the RF-CMOS requirements of the International Technology Roadmap for Semiconductors. FoM projections for basic RF building blocks (low-noise amplifier and oscillator) show that good performance can already be obtained with simple circuit topologies. The main advantage of CNFET circuits yet lies in easily reaching operation frequencies of several hundreds of gigahertz, which are hard to be exploited by silicon technologies at similar technology nodes.Postprint (published version

A compact noise model for carbon nanotube FETs

This paper focuses on the development of a compact noise model for radiofrequency (RF) carbon nanotube field-effect transistors (CNFET). The noise mechanisms in these devices are discussed and the impact of the different noise sources is analyzed. For the RF-CNFET under investigation a mínimum noise figure NFmin = 0.104 dB at 60 GHz is predicted. Our model is usable with conventional circuit simulators, which provides a basis for further investigations on CNFET-based RF Building blocks.Peer Reviewe

Radio-Frequency Performance of Carbon Nanotube-Based Devices and Circuits Considering Noise and Process Variation

This paper provides a global overview of the radiofrequency (RF) performance potential of carbon-nanotube field-effect transistors (CNFET), which for the first time includes the impact of noise. We develop noise and manufacturing process variability extensions for the Stanford CNFET compact model, implemented in Verilog-A and compatible with conventional circuit simulators. CNFET figures-of-merit (FoM) are determined both on the device and on the circuit level. Compared to silicon technology, CNFET devices show much better performance in terms of most of the RF-CMOS requirements of the International Technology Roadmap for Semiconductors. FoM projections for basic RF building blocks (low-noise amplifier and oscillator) show that good performance can already be obtained with simple circuit topologies. The main advantage of CNFET circuits yet lies in easily reaching operation frequencies of several hundreds of gigahertz, which are hard to be exploited by silicon technologies at similar technology nodes

Carbon nanotube FET process variability and noise model for radiofrequency investigations

This work focuses on process variability and noise in carbon nanotube field-effect transistors (CNFET) to obtain a compact model usable for radiofrequency (RF) design and simulations. CNFET figures of merit (FoM) are determined and compared to International Technology Roadmap for Semiconductors (ITRS) requirements on conventional analog silicon-based devices. The developed model is also used to investigate on the impact of manufacturing process variability on the CNFET's RF-performance and noise behavior

An accurate and Verilog-A compatible compact model for graphene field-effect transistors

The present paper provides an accurate drift-diffusion model of the graphene field-effect transistor (GFET). A precise yet mathematically simple current-voltage relation is derived by focusing on device physics at energy levels close to the Dirac point. With respect to previous work, our approach extends modeling accuracy to the low-voltage biasing regime and improves the prediction of current saturation. These advantages are highlighted by a comparison study of the drain current, transconductance, output conductance, and intrinsic gain. The model has been implemented in Verilog-A and is compatible with conventional circuit simulators. It is provided as a tool for the exploration of GFET-based integrated circuit design. The model shows good agreement with measurement data from GFET prototypes.Peer Reviewe

The surgical safety checklist and patient outcomes after surgery: a prospective observational cohort study, systematic review and meta-analysis

© 2017 British Journal of Anaesthesia Background: The surgical safety checklist is widely used to improve the quality of perioperative care. However, clinicians continue to debate the clinical effectiveness of this tool. Methods: Prospective analysis of data from the International Surgical Outcomes Study (ISOS), an international observational study of elective in-patient surgery, accompanied by a systematic review and meta-analysis of published literature. The exposure was surgical safety checklist use. The primary outcome was in-hospital mortality and the secondary outcome was postoperative complications. In the ISOS cohort, a multivariable multi-level generalized linear model was used to test associations. To further contextualise these findings, we included the results from the ISOS cohort in a meta-analysis. Results are reported as odds ratios (OR) with 95% confidence intervals. Results: We included 44 814 patients from 497 hospitals in 27 countries in the ISOS analysis. There were 40 245 (89.8%) patients exposed to the checklist, whilst 7508 (16.8%) sustained ≥1 postoperative complications and 207 (0.5%) died before hospital discharge. Checklist exposure was associated with reduced mortality [odds ratio (OR) 0.49 (0.32–0.77); P\u3c0.01], but no difference in complication rates [OR 1.02 (0.88–1.19); P=0.75]. In a systematic review, we screened 3732 records and identified 11 eligible studies of 453 292 patients including the ISOS cohort. Checklist exposure was associated with both reduced postoperative mortality [OR 0.75 (0.62–0.92); P\u3c0.01; I2=87%] and reduced complication rates [OR 0.73 (0.61–0.88); P\u3c0.01; I2=89%). Conclusions: Patients exposed to a surgical safety checklist experience better postoperative outcomes, but this could simply reflect wider quality of care in hospitals where checklist use is routine